module test (
    input logic[7:0] a_in,
    output logic[7:0] b_out
);
    assign b_out=a_in+1;
    
endmodule



module testbench; 
parameter PERIOD =10 ;

function int mytest(int a);
    mytest = a+1;
    $display("func finish");  
endfunction

logic[7:0] a_in;
logic[7:0] b_out;

test t_ins(.*);

initial begin
    $display("\033[32m\t\t!!\tcode begin\t!!");  
    // for (int i =0 ;i<5 ;i++ ) begin 
    //     $display("a =%0d",i);  
    //     $display("fa=%0d",mytest(i)); 
    // end
    #(PERIOD) a_in=0;
    #(PERIOD) $display("a =%0d",b_out); 
    #(PERIOD) a_in=1; 
    #(PERIOD) $display("a =%0d",b_out); 
    #(PERIOD) a_in=2;
    #(PERIOD) $display("a =%0d",b_out); 

    $display("\t\t!!\tcode end\t!!\033[0m");
    $finish; 
end 
endmodule 